Design Verification Engineer, New Grad

SambaNova · San Jose

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Company
SambaNova
Location
San Jose
Salary
$120,000 — $150,000
Posted
October 27, 2026

About this job

About the Team The Design Verification team verifies the RDU, SambaNova's chip for AI workloads. We build SystemVerilog and UVM environments for chip-level control and initialization, including sequencing, state transitions, clocking, and recovery, and work with architects, RTL designers, and firmware engineers. About the Role As a new grad Design Verification Engineer, you'll write testbenches, tests, checkers, and coverage in SystemVerilog and UVM for RDU features. You'll run regressions, debug simulation failures, and work with RTL designers to find and fix bugs before tape-out. Responsibilities Write and execute verification plans for chip-level control and initialization features Build SystemVerilog and UVM testbench components, including sequences, checkers, assertions, and…

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