ASIC DFT STA Engineer

Cisco · San Jose

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Company
Cisco
Location
San Jose
Employment type
Full-time
Posted
October 23, 2026

About this job

We are seeking an ASIC DFT SDC Engineer to drive the development of next-generation networking chips. You will focus on timing constraint analysis, RTL design, and SDC development, collaborating with cross-functional teams. Ideal candidates bring strong analytical skills and significant experience in timing constraint verification and programming.

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