Senior ASIC RTL Engineer

Cisco · San Jose

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Company
Cisco
Location
San Jose
Employment type
Full-time
Salary
$167,700.00 to $245,200.00
Posted
October 20, 2026

About this job

Your primary focus will be to drive high-quality Design for Test (DFT) RTL, ensuring robust and reliable silicon solutions that meet Cisco’s standards for performance and innovation. This cross-functional teamwork is essential to delivering advanced networking silicon aligned with Cisco Silicon One’s scalable and flexible architecture. Minimum Qualifications: Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 7 years of experience Prior experience in Verilog/System Verilog coding. Prior experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification). Prior experience with industry standard interface protocols such as AMBA(AXI, APB, AHB), JTAG etc, memories.…

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