PhD Research Fellow in Multi-Level Resistive Memory Cells for Ternary Computing

About this job

https://vimeo.com/898549899/60305e2540 About the position The Faculty of Technology, Natural Sciences and Maritime Sciences invites applications for a 100% PhD Research Fellow position in fabrication and characterization of multi-level resistive memory technology. The position is a three-year, full-time research appointment with no teaching obligations. The doctoral programme in Technology comprises approximately six months (30 ECTS) of coursework, an article-based thesis demonstrating independent research, active participation in national and international research environments, research dissemination, a trial lecture, and public defence. Read more in our PhD handbook. Admission to the Faculty's doctoral programme in Technology must be applied for and granted within three months of starting the position. The place of work is at Campus Vestfold (Raveien 215, Borre, Norway. Located on campus is the MST-lab, part of the national NorFab infrastructure for fabrication and characterization. Your personnel manager will be Marius Tannum (Head of department, Microsystems, Campus Vestfold). About the doctoral project Resistive memory (ReRAM, also known as memristors) has matured rapidly. It offers fast writes at lower power, has high endurance and non-volatile retention. Recently Nordic Semiconductor released the nRF54L microcontroller series which feature binary ReRAM to replace flash memory at scale. Multi-level operation, however, remains challenging with device-to-device and cycle-to-cycle variation, state drift, read disturbs and non-linear multi-state programming. This PhD project aims to address these issues by fabricating and characterizing ReRAM cells optimized for balanced ternary (symbols -1, 0 and 1), storing ~58% more information per cell than binary. This enables exciting applications like ternary neural networks, ultra-efficient event-based cameras, high-density storage and mixed-radix 3D SoCs. Building on our preliminary work with 3-level ReRAM devices you will mainly work on task 1, with a possibility to work on task 2 in parallel. Task 1: Fabrication of ternary ReRAM cells. ReRAM cells are metal-insulator-metal (MIM) stacks that can be deposited by sputtering or atomic layer deposition. Making a functional multi-level device that is reliable with three (or powers of three) well separated resistance levels and is reproducible at wafer scale is the main challenge. You will fabricate and characterize the devices in USN’s MST fab in Vestfold and can use other Norfab cleanroom infrastructure if necessary. Extensive characterization activities (pulsed and DC I-V, retention, endurance, device-to-device variability, etc.) are expected using automated measurements setups and with carefully designed experiments to turn the raw data into publishable insights. Task 2: Design of an on/off-chip ternary ReRAM controller. You will design mixed-signal, mixed-radix circuitry for writing and reading radix-3 states on commercially available ReRAM devices with the devices from task 1 as the long-term target. The digital control logic for radix-3 states can be written in ternary HDL using our group’s EDA tools (MRCS Studio) and ternary RTL-to-GDS synthesis flows. For this task you will use commercial foundries to tape-out and validate correct operation for a selection of suitable ReRAM devices. You will join USN’s Ternary Research Group, founded in 2019 by Assoc. Prof. Steven Bos and Assoc. Prof. Henning Gundersen. The research group provides an active research environment which includes MSc students and PhD research fellows working on carbon nanotube-based (CNTFET) switching devices and sensors compatible with ternary logic. Qualifications Eligibility Requirements: A Master’s degree (120 ECTS) or equivalent higher education qualifications in Micro/Nanoelectronics, Electronic/Electrical Engineering, Nanotechnology, Materials Science and Engineering, Physics or related fields. The master’s degree must have been obtained by the application deadline for the position. Strong background in electronics, chip design, microfabrication and / or material science. Weighted average grade of B or higher on the master’s degree and thesis. Excellent written and spoken English with documented proficiency. Ideal applicants have: Hands-on experience in cleanroom environment for microfabrication or comprehensive knowledge of microfabrication fundamentals. Good understanding of CMOS chip design flows, or proficiency in relevant EDA tools such as Cadence Virtuoso, (H)SPICE simulation Experience in electrical characterization (probe station, DC and pulsed I-V, retention and endurance testing, instrument automation) Experience writing Verilog-A and/or RTL in (System)Verilog or VHDL Relevant master’s thesis or major projects aligned

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