Verification Engineer
Ubitium GmbH · Rülzheim
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- Company
- Ubitium GmbH
- Location
- Rülzheim
- Posted
- August 25, 2026
About this job
Tasks Build cocotb-based testbenches for RTL blocks ranging from complicated datapaths to multilevel interconnect, driven by property-based test generation rather than fixed directed vectors.Write SystemVerilog Assertions (SVA) to catch protocol violations directly in simulation, plus cover property statements to close functional-coverage gaps. Cross-check RTL behavior against independent golden reference models (including formally-specified models) to catch divergence between spec intent and implementation Drive functional coverage closure, reviewing coverage reports Debug failures using waveform viewers and simulator transcripts, working from a failing assertion or model mismatch back to a root cause in the RTL, the testbench, or the model.…
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Engineer salaries in Germany
Based on 332 postings that disclose pay.
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