Technical Lead, Power Analysis and Optimization
Cisco · San Jose
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- Company
- Cisco
- Location
- San Jose
- Employment type
- Full-time
- Posted
- September 10, 2026
About this job
We are recruiting a Technical Lead, Front-End Power Optimization to oversee fullchip SDCs and collaborate with design teams to refine timing constraints for next-generation networking chips. The role requires strong ASIC design expertise and experience with SDC/STA tools, ideal for candidates with significant ASIC or related experience.
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