Processor Design Engineer

Über diese Stelle

Cache, Memory Management Unit (MMU), Multi-Core & Bus Coherence, Branch Prediction, Debug & Test Structures. Prospective team members require experience in at least one focus area; strong Verilog/SystemVerilog skills; RISC-V experience preferred. Requirements Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role. Relocation required. Currently 4 days on-site, 1 day remote. Policy may change. We have multiple openings. Benefits Competitive salary plus stock options 30+ days of paid vacation Relocation support Full German social security and universal healthcare A modern office Free snacks, coffee, and drinks Work with people who actually know their stuff – computer architects, hardware nerds, and engineers who love tough problems.…

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