Synthesis Engineer

Über diese Stelle

synthesis, STA, timing closure, place & route and/or sign-off. Prospective team members require strong Verilog/SystemVerilog; STA expertise; SDC; synthesis/STA tools preferred. Requirements Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role. Relocation required. Currently 4 days on-site, 1 day remote. Policy may change. Benefits Competitive salary plus stock options 30+ days of paid vacation Relocation support Full German social security and universal healthcare A modern office Free snacks, coffee, and drinks Work with people who actually know their stuff – computer architects, hardware nerds, and engineers who love tough problems. A culture where new ideas matter, but so does respect and collaboration.…

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